1. Field of the Invention
This invention relates to active matrix drive circuits and is concerned more particularly, but not exclusively, with drive circuits for active matrix liquid crystal displays (AMLCD'S).
The invention can be applied, for example, to drive circuits for driving matrix-addressed grey-scale thin-film display panels, such as AMLCD'S, with digital data, and can be implemented in a compact and area efficient manner. The circuit can be constructed with conventional large scale integration (LSI) to form chip-on-glass (COG) data drive circuits, although the circuit offers particularly significant advantages in terms of area efficiency when implemented using thin-film transistors (TFT) integrated on the display substrate.
2. Description of the Related Art
FIG. 1 shows a typical AMLCD 1 composed of N rows and M columns of pixels addressable by scan lines 2 connected to a scan line driver circuit 3 and data lines 4 connected to a data line driver circuit 5. Data voltages are applied to the data lines 4 by the data line driver circuit 5 and scan voltages are applied to the scan lines 2 by the scan line driver circuit 3 so that such voltages in combination serve to apply analogue data voltages to the pixel electrodes 6 (as best seen in the enlarged detail of the display in the lower half of the figure) in order to control the optical transmission states of the pixels along each row as the rows are scanned in a cyclically repeating sequence. This is achieved as follows for a single row of pixels. The data line driver circuit 5 reads serial analogue or digital data to be displayed by the row of pixels, and applies parallel analogue data voltages to the data lines 4 so as to charge up each data line 4 to the required data voltage. The scan line 2 corresponding to the row of pixels to be controlled is activated by the application of the scan voltage by the scan line driver circuit 3 so that a TFT 7 associated with each pixel is switched on to transfer charge from the corresponding data line 4 to a pixel storage capacitance 8 (as shown in broken lines in the figure) associated with the pixel. When the scan voltage is removed the TFT 7 isolates the pixel storage capacitance 8 from the data line 4 so that the optical transmission state of the pixel corresponds to the voltage across the pixel storage capacitance 8 until the pixel is refreshed during the next scanning frame. The rows of pixels are refreshed one at a time until all the rows have been refreshed to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
The data line driver circuit 5 for such a display can be implemented using conventional LSI and bonded to the periphery of the display using COG techniques, or alternatively the circuit can be fabricated monolithically on the display substrate using polysilicon TFT circuitry. However, since the data line driver circuit 5 of such a display requires more sophisticated circuitry than the scan line driver circuit 3, it will be apparent that it is the form of circuit used for the data line drive which will have the more significant impact on the viability of implementing the drive electronics using monolithic low performance TFT circuitry.
The most straightforward driving scheme for such a display is the point-at-a-time driving scheme, and FIG. 2 shows an analogue data line driver circuit 10 which may be employed in such a driving scheme. In this circuit 10 a shift register composed of a chain of D-type flip-flops 11 is connected so that the output of each flip-flop 11 controls the gate of an associated sampling transistor 12 for sampling the analogue video input signal AVIDEO and for applying the sampled signal to the corresponding data line 4 with its associated parasitic capacitance, shown in broken lines at 13 in the figure. For a colour display there are three analogue video lines, one for each RGB signal. In operation frame and line synchronisation pulses VSYNC and HSYNC indicate the start of a frame period and a line period respectively, and a clock signal CK at the sampling frequency is applied to the clock inputs of the flip-flops 11 so that a circulating "1" state within the shift register sequentially activates the sampling transistors 12 at the sampling frequency. The RC time constant formed by the on resistance of the sampling transistor 12 and the resistance and distributed capacitance of the data line 4 must be sufficiently less than the available sampling period (1/fNM) for the sampling to be executed successfully.
FIG. 4a is a timing diagram showing the timing of the signals associated with such a point-at-a-time data line driver circuit 10, where S1, S2 and S3 refer to the scan voltages applied to the first three scan lines numbered from the top of the display. It will be noted that the AVIDEO signal is sampled at the same time as application of the data voltages to the pixels on activation of the scan lines in successive scanning line periods T1, T2 . . . by the scan voltages S1, S2, S3, such scan voltages being synchronised by the HSYNC pulses. In order to increase the length of the sampling window, it is possible to use multiple phase timing registers which sample a multiphase analogue input signal. However a realistic limit of four phases restricts the point-at-a-time driving scheme to relatively small displays having low capacitance data lines, or alternatively low resolution displays having a slow data rate.
For analogue displays of large size or high, pixel resolution, in which the RC time constant of the data lines is larger than the available sampling window for the point-at-a-time driving scheme, it is necessary for a line-at-a-time driving scheme to be used instead, and FIG. 3a shows an analogue data line driver circuit 20 which may be employed in such a driving scheme. In this circuit 20 a shift register composed of a chain of D-type flip-flops 21 is connected so that the output of each flip-flop 21 controls an associated sampling circuit 22 for sampling the AVIDEO signal and applying the sampled signal to the corresponding data line 4 with its associated parasitic capacitance, shown in broken lines at 23 in the figure. As shown in the enlarged detail of FIG. 3b, each of the sampling circuits 22 supplied with control signals by a control circuit 24 comprises two control gates 25 and 26, two small storage capacitors 27 and 28, and a buffer 29. In each case the capacitor 27 or 28 is employed to store a sample of the AVIDEO signal, and the voltage on each capacitor is then transferred to the data line by the buffer 29. Two storage capacitors 27 and 28 are normally sued since the sampling of the serial input data and the driving of the data lines cannot take place simultaneously. While the capacitor 27 is being used for sampling, the capacitor 28 and the buffer 29 are driving the data line. During the next line period, the capacitor 27 and buffer 29 are used to drive the data line, whilst the capacitor 28 is used for the next line sample. Thus, at any one instant, a whole line of video data is stored in the analogue memory consisting of the capacitors 27 and 28.
FIG. 4b is a timing diagram showing the timing of the signals associated with such a line-at-a-time data line driver circuit 20, for comparison with the point-at-a-time timing diagram of FIG. 4a. the important feature of the line-at-a-time driving scheme is that the scan line is activated only after a complete line of data has been sampled during line period T1, the next complete line period T2 being used for scanning of the data to the pixels as well as sampling of the data for the row of pixels (as opposed to the point-at-a-time driving scheme of FIG. 4a where sampling and scanning occur in each of the line periods T1 and T2). However the implementation of the line memory and buffering incurs a significant overhead both in terms of numbers of components and drive circuit complexity.
There is an increasing trend within the field of active matrix displays to adopt a digital interface to the external video source. Such a digital interface is in general more robust to noise and offers considerable simplifications in terms of system design. Digital data line driver circuits normally use a line-at-a-time driving scheme and require a line memory, and a number of such circuits are disclosed by A. Lewis, "Driver circuits for AMLCD's", Journal, pages 56-64, 1993 and C. Reita, "Integrated driver circuits for active matrix liquid crystal displays", Displays, Vol. 14(2), pages 104-114, 1993. FIG. 5 shows a typical digital data line driver circuit 30 comprising an input register 31 in the form of a first row of n-bit digital latches constituting a line memory, a storage register 32 in the form of a second row of n-bit digital latches, and a row of digital-to-analogue (D/A) converters 33 for applying voltages to the data lines 4 by way of output buffers 34. The input register 31 is used to sample the n-bit parallel input data under control of a timing register 35 supplied with control signals. Once a line of data has been loaded into the input register 31, the data is transferred to the storage register 32 to enable digital-to-analogue conversion to be effected by the D/A converters 33, leaving the input register 31 free to concurrently sample a new line of data. The use of the two registers 31 and 32 provides a pipeline delay equal to one line period during which the digital-to-analogue conversion and line driving can take place.
Within this basic framework, the differences between the various known drive circuits principally relate to the method of D/A conversion and line driving. FIG. 6 shows the simplest type of D/A converter which is in the form of an unbuffered parallel switched capacitor array, as disclosed by, for example, Y. Matsueda, S. Inoue, S. Takenaka, T. Ozawa, S. Fujikawa, T. Nakazawa and H. Ohschima, "Low temperature poly-Si TFT-LCD with integrated 6-bit digital data drivers", Society for information Display 96 Digest, pages 21-24, and U.S. Pat. No. 5,251,051. In this circuit each D/A converter 33 comprises an array of n capacitors 36 and associated switches 37, the capacitors 36 having binary weighted capacitances Co, 2Co . . . 2.sup.n-1 Co. The capacitors 36 are charged to a reference voltage in accordance with the digital data and subsequently connected directly to the data lines 4 by transfer switches 38. There are a number of drawbacks with this approach, including the area required for the capacitor array and digital storage and also the limitation on line capacitance and hence display panel size. Since the line capacitance is driven purely by charge sharing, it is apparent that this type of circuit is only suitable for relatively small displays.
In order to drive the capacitative loads associated with displays of larger size or higher resolution, it is possible to add a buffer between the binary weighted capacitor array and the line capacitance, as disclosed in U.S. Pat. No. 5,453,757. FIG. 7 shows an example of this type of converter, as disclosed by A. Lewis, "Driver circuits for AMLCD's", Journal, pages 56-64, 1993. In this case a buffer amplifier 39 and large feedback capacitor 40 are required for each converter 33, and this further increases the area required for implementation of the converter 33. Furthermore the feedback capacitor 40 is generally made equal to the sum of the input capacitance in the binary array and thus the buffer amplifier 39 has a significant load to drive.
The large area overhead of such parallel switched capacitor D/A converters has limited the use of such converters, especially for display panels with monolithic data drivers. A number of alternative converter arrangements have been proposed, the most popular of which is the sampled ramp converter as disclosed in U.S. Pat. No. 5,457,415 and as shown in FIG. 8. In this circuit the outputs of the storage register 32 for each data line 4 are supplied to a comparator 42 which controls the state of a switch 43 connecting a global ramp signal to the data line 4. The comparator 42 compares the contents of the storage register 32 with a global count signal supplied by way of a line 44 and maintains a connection between the ramp signal and the data line 4 only whilst the current global count is less than the contents of the storage register 42. Once the global count has exceeded the contents of the storage register 32, the ramp signal is disconnected from the data line 4 to leave the desired data voltage on the line capacitance. The main disadvantages of such a circuit are the large area required for its implementation and the need to supply an external ramp signal.